1. Technical Field
The present invention relates to the field of processor task scheduling, and more specifically, to a hardware real-time scheduler implementing a memory monitoring methodology.
2. Description of the Related Art
Real-time applications such as video processing applications and embedded control systems and often require high resolution timing and scheduling, which leads to small operation system (OS) timer ticks and greater scheduling overhead for a processor. In other words, a greater portion of processing time is spent determining task schedules rather than processing tasks. Overhead for task scheduling and time management typically increases linearly with system clock frequency.
Therefore, scheduling and time management may be offloaded to hardware such as a coprocessor, field-programmable gate array (FPGA), etc. The offload hardware may calculate/determine task schedules without consuming processor cycles, allowing a processor or central processing unit (CPU) more time to execute currently scheduled tasks. The offload hardware may maintain various implementations of a run queue to efficiently select next schedulable tasks for the CPU. Examples of scheduling policies for run queues include rate monotonic, earliest deadline first, least laxity first, etc., and are beyond the scope of the present disclosure.
Typically, offload hardware provides a next schedule of tasks to a CPU in one of two ways. First, the offload hardware may interrupt the CPU when it determines that it is time to execute a different task on the CPU. Second, the CPU may read from the offload hardware when a CPU timer interrupt fires. In both cases an interrupt service routine typically reads the next schedule from the offload hardware. However, a CPU typically performs a context switch before executing an interrupt service routine, which adds to CPU overhead. Further, servicing an interrupt generally requires other context switches such as loading a new context after exiting an interrupt service routine. Finally, the time interval between a point when an interrupt fires and a point when the interrupt service routine is invoked may vary based on CPU execution state before the context switch.